1. Field of the Invention
The present invention relates generally to a method for fabricating a semiconductor device and more particularly to a method for forming trench isolation having the step of enhancing the bonding force between the sidewall silicon dioxide layer and the sidewall of the trench.
2. Description of the Prior Art
Techniques such as local oxidation of silicon (LOCOS) and selective polysilicon oxidation technology (SEPOX) have been used to decouple the metal oxide semiconductor (MOS) transistors created on a silicon substrate. However, as these circuits become highly integrated, these conventional isolation techniques are not available, since they are limited to devices with a linewidth under 0.35 .mu.m. The application of silicon etching, so called trench etching technology, has emerged with the need for a deeper (3.0 .mu.m or more) and narrower (1.25 .mu.m or less) slots or trenches in a silicon substrate.
Generally, a trench is used to isolate devices in complementary MOS (CMOS) and bipolar circuits. Vertical capacitors or transistors can also be fabricated inside the trench. The ideal trench has inwardly sloped walls and a rounded bottom. The sloped wall, caused by redeposition during etching, is necessary to eliminate the formation of a void in the trench during the conformal deposition process. The rounded bottom is desirable to eliminate an electric field concentration.
This trench isolation process can proceed in the standard CMOS process. This trench isolation structure can be formed on and in the epitaxial silicon substrate. The trench is etched deep enough to penetrate through the epitaxial layer, which effectively decouples the bipolar transistors.
FIG. 1 is a flow chart of a conventional method for forming a trench isolation structure. As shown in FIG. 1, a silicon dioxide layer (SiO.sub.2) is initially deposited on the silicon substrate (Si), and then a silicon nitride layer and a hard mask are deposited thereon in succession (Step 61). The hard mask is a silicon dioxide layer formed by high temperature oxidation. This hard mask serves as an etching mask against reactive ion etching.
The silicon dioxide layer, silicon nitride layer, and hard mask are then selectively removed to expose the underlying silicon substrate by photo etching to form a trench (step 62). After the photo etching process, an ashing/strip process for removing the photoresist ensues. The layers of silicon nitride and hard mask are defined and then used as an etching mask during a dry etching of the silicon substrate to form a deep and narrow trench (step 63). A reactive ion etching method is commonly used for this dry etching. In reactive ion etching, the physical etch rate is higher than the chemical etch rate.
After the trench is formed, a sidewall of silicon dioxide is grown to form an insulating layer by sidewall oxidation (step 64). The sidewall silicon dioxide layer is provided to protect the exposed sidewall of the trench and serves as an autodoping barrier between an active region and a field region. The trench is then filled with an insulator by depositing two or more thin films. After this, the plasma enhanced tetraethylorthosilicate (PE-TEOS) layer is then formed (step 65). The PE-TEOS layer is first deposited on the silicon substrate and sidewall of the trench (step 65a), and then the PE-TEOS layer around the entrance of the trench is etched back using argon gas (step 65b). The etchback process (step 65b) makes the entrance of the trench wider and simplifies the process of filling the trench.
Due to the action of plasma during the etchback process (step 65b), the surface of the PE-TEOS layer becomes rough. Therefore, an NH.sub.3 plasma treatment (step 66) is provided to make the surface of the PE-TEOS layer smooth by removing the impurities deposited on the PE-TEOS layer and to enhance the bonding force between the PE-TEOS layer and an ozone TEOS (O.sub.3 -TEOS) layer that will be deposited on the PE-TEOS layer.
The O.sub.3 -TEOS layer and another PE-TEOS layer are deposited on the silicon substrate and sidewall of the trench at step 67, and finally an annealing process 68 follows. The annealing process 68 occurs at about 1050.degree. C. under N.sub.2 atmosphere for about 60 minutes.
The disadvantages of the method for forming trench isolation using a trench etching process (step 63) are as follows:
First, the bonding between the sidewall of the trench and the sidewall silicon dioxide layer may become weaker during the trench etching process (step 63) and the etchback process (step 65b) due to the effect of plasma on the sidewall of the trench.
Second, the sidewall silicon dioxide and sidewall of the trench (SiO.sub.2 -Si) interface can get separated. This separation at the SiO.sub.2 -Si interface is caused by thermal shrink during annealing (step 68) or by the oversaturation of ions or atoms in the SiO.sub.2 -Si interface while filling the trench with an insulator.
Thus, these defects at the SiO.sub.2 -Si interface may occur when trench isolation is formed according to a conventional process. Due to the defects such as dislocation and well leakage point, a resulting semiconductor chip may not operate correctly.
FIG. 2 is a schematic drawing of a vertical scanning electron microscope (V-SEM) cross-sectional view of a trench. As shown in FIG. 2, a void 15 has been formed between the silicon substrate 10 and the sidewall silicon dioxide layer 12. This void 15 has its origin in the material formed at the SiO.sub.2 -Si interface 11 or in the separation at the SiO.sub.2 -Si interface 11. If the etch rate of the material formed at the SiO.sub.2 -Si interface 11 is higher than that of the sidewall silicon dioxide 12a and the silicon substrate 10, this material is etched away in advance of the sidewall silicon dioxide 12a and the silicon substrate 10 during the chemical process for V-SEM analysis. That is the reason why the SiO.sub.2 -Si interface 11 is susceptible to damage.
FIG. 2 shows a silicon dioxide layer 12 on the silicon substrate 10, a silicon nitride layer 14, a hard mask 16, and a trench 13 filled with insulator 17. The insulator 17 may contain such materials as PE-TEOS 17c, O.sub.3 -TEOS 17b, and PE-TEOS 17a.